Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to technology for stabilizing a high-speed operation of a semiconductor memory device by outputting a clocking pattern through an inversion pin.
There are several methods for stabilizing a high-speed operation in a semiconductor memory device. The methods include a method of monitoring a channel transmission error of read/write data like a cyclic redundancy check, and a method of checking the setup/hold of signals that are transmitted between a memory controller, e.g., a graphics processing unit (GPU) in case of a graphic memory device, and a memory device as in address/read/write training.
The methods further include a method of continuously transmitting information for a clock used in the memory device to the memory controller. In this method, if the memory device continuously transmits the information for the clock used therein to the memory controller, the memory controller can grasp the variation of temperature or voltage within the memory device immediately.
As the method of transmitting the clock information within the memory device, there is an EDC (Error Detection Code) hold pattern employed in a graphic memory device. This method is to repeatedly output a 4-bit hold pattern having the clock information to an EDC pin except in self-refresh/RDQS/reset/power-down modes and in the cases that CRC data are loaded on a bus and an internal WCK is unstable. If the hold pattern is constructed to be continuously toggled so as to produce an output pattern like 0101, the hold pattern outputted to the EDC pin has the information for the clock used in the memory device.
CRC (cyclic redundancy check) data are outputted to the EDC pin while read data are outputted from the memory device. Therefore, since the EDC hold pattern is not outputted while the read data are outputted, there is a concern that the clock information of the memory device may not be outputted to the outside of a chip. If the hold pattern is outputted through the EDC pin while the read data are outputted, it is possible to output the clock information of the memory device to the outside of the chip while the read data are outputted. However, in this case, the CRC data are not outputted and thus it is impossible to detect an error in the read data.
In accordance with the present invention, a data bus inversion (DBI) pin is used to overcome the above-discussed drawbacks. Hereinafter, a role and the constitution of the inversion pin DBI used in a memory device will be described.
FIG. 1 is a block diagram illustrating a peripheral circuit of the inversion pin DBI in a conventional memory device.
The inversion pin DBI is employed to input/output inversion information that constitutes information about whether data inputted/outputted through a data pin DQ are inverted or not. In a write operation, inversion information WDBI is inputted to the memory device from the outside. In a read operation, inversion information RDBI is outputted from the memory device.
As described in FIG. 1, the peripheral circuit includes a selecting unit 110, a parallel-to-serial converting unit 120, an output driver 130, a termination resistor 140, an input buffer 150, and a serial-to-parallel converting unit 160.
The selecting unit 110 plays a role of determining the signal inputted to the parallel-to-serial converting unit 120 depending on conditions. That is, the selecting unit 110 selects the inversion information RDBI in the read operation and write training data WRITE_TRAINING_DATA in a write training operation. Moreover, in a read training operation, read training data READ_TRAINING_DATA are selected. For reference, the read training data READ_TRAINING_DATA are inputted from the outside of the chip together with a pattern loading instruction LDFF.
The parallel-to-serial converting unit 120, also referred to as a first-in-first-out (FIFO), serially arranges signals inputted thereto in parallel. Since FIG. 1 illustrates a memory device using 8-bit pre-patch, the parallel-to-serial converting unit 120 described in FIG. 1 arranges 8 parallel signals into series signals. The parallel-to-serial converting unit 120 operates in sync with a clock CLK. Therefore, since there is no need for the inversion pin DBI to input/output the inversion information while the data are not inputted/outputted through the data pin DQ, the clock CLK used for the parallel-to-serial converting unit 120 is generally designed to be only enabled while the data are inputted/outputted, i.e., in the read/write operation, thereby reducing current consumption. A signal CENTER_CLKEN in FIG. 1 is employed to control the clock CLK inputted to the parallel-to-serial converting unit 120 as described above. Thus, the clock CLK inputted to the parallel-to-serial converting unit 120 is toggled while the signal CENTER_CLKEN is enabled and not toggled while the signal CENTER_CLKEN is disabled. A signal POUT_CLB controls the inversion information RDBI to be outputted corresponding to the column address strobe (CAS) latency (CL) and thus determines the timing that data arranged by the parallel-to-serial converting unit 120 are transmitted to the output driver 130.
The output driver 130 plays a role of outputting a signal outputted from the parallel-to-serial converting unit 120 to the outside of the chip using the inversion pin DBI.
The termination resistor 140 is employed for the impedance matching of the inversion pin DBI. Since the output driver 130 outputting the inversion information can perform the impedance matching by itself, the termination resistor 140 is only turned on while the inversion information is inputted through the inversion pin DBI. A signal ODTEN in FIG. 1 is to turn on/off the termination resistor 140 and is enabled to turn on the termination resistor 140 when the inversion information is inputted from the outside.
The input buffer 150 receives the inversion information WDBI inputted through the inversion pin DBI and the serial-to-parallel converting unit 160 arranges the inversion information WDBI in parallel and transmits the arranged information to the inside of the memory device.